Ants · legend

The green/black/red rigid board with copper traces. The physical substrate every electronic device is built on.

A PCB with components soldered on. "Bare PCB" + reflow = PCBA.

The electrical diagram. Shows *which* parts are connected to which, ignores physical layout.

The physical drawing. Where each part sits on the board, how copper traces run between them.

A copper line on the PCB that carries a signal or power.

A plated hole that connects copper on one layer to copper on another.

A small area of exposed copper where a component is soldered.

The pattern of pads that matches a specific chip package.

Any group of pads/pins that are electrically connected. "VCC net," "GND net," "USB_DP net."

One sheet of copper. 2-layer = top + bottom; 4-layer = top + 2 inner + bottom.

The insulating material between copper layers. Usually FR4 fiberglass.

The white (or other color) printed text/lines on the PCB. Labels, logos, component references.

The green (or black/red/blue) lacquer covering the board, with holes only where pads need solder.

2-wire bus (SDA + SCL), multi-drop, slow (100 kHz–1 MHz), needs pull-up resistors.

4-wire bus (SCK + MOSI + MISO + CS), point-to-point per device, fast (10–50 MHz).

2-wire serial (TX + RX), no shared clock, classic "serial console."

The standard you plug into your laptop. Power + data on one cable.

The reversible connector + cable spec; one of the connector options for USB.

The protocol that lets USB-C negotiate voltages above 5 V (up to 20 V, 5 A).

Robust 2-wire bus used in cars, robotics. CAN-FD is the faster modern version.

Industrial differential serial bus. Long cable runs, multi-drop, noise-tolerant.

High-rate industrial fieldbus for distributed motion control.

SPI with 4 data lines instead of 1 — 4× the bandwidth. Used for flash memory.

High-speed differential buses for cameras and displays.

The bus used by SSDs, GPUs, M.2 cards. Very high-speed differential.

The data wire in I²C.

The clock wire in I²C.

The clock wire in SPI.

SPI data wire from controller → chip.

SPI data wire from chip → controller.

SPI line that tells a specific chip "I'm talking to you now."

A pin a chip pulls low/high to say "hey, I have new data ready."

Common names for the positive supply rail. Used interchangeably.

Separate supply specifically for a chip's input/output pins (can differ from core voltage).

The raw incoming voltage before any regulation.

The reference 0 V rail. Every signal is measured relative to it.

Linear voltage regulator. Cheap, simple, inefficient at large voltage drops.

Switching regulator that steps voltage *down* efficiently. Needs an inductor.

Switching regulator that steps voltage *up*.

Handles input both above and below the output. Used in battery-powered devices.

A single chip that does many regulators + sequencing. Common with SoCs.

Small ceramic capacitor placed next to a chip's power pin to smooth out current spikes.

Larger capacitor (10 µF+) that supplies slower current changes.

Clamps voltage spikes (lightning, ESD) to a safe level.

Resettable fuse — opens on overcurrent, resets when it cools.

A voltage-controlled switch. Used in regulators, motor drivers, reverse-polarity protection.

A P-channel MOSFET (or diode) that prevents damage if the battery is plugged in backwards.

An unbroken copper area on one layer dedicated to GND. The single most important layout rule.

A complete tiny computer on one chip: CPU + RAM + peripherals.

A larger MCU with more compute and peripherals (e.g. Rockchip RK3588).

A small PCB with an SoC + RAM + flash, sold as a drop-in module (e.g. Jetson Orin).

A chip whose digital logic you wire up in software.

Converts an analog voltage into a digital number.

The reverse — turns numbers into voltages.

Circuit that multiplies a low-frequency clock into a higher one (e.g. 12 MHz xtal → 133 MHz CPU).

Chip that measures motion (accelerometer + gyro, sometimes magnetometer).

How many independent motion axes a sensor measures. 6-DoF = 3 accel + 3 gyro; 9-DoF adds 3 magnetometer.

A 9-DoF IMU + sensor-fusion algorithm that outputs orientation in 3D.

The kind of motor used in drones, robots, EVs.

Circuit that monitors and protects a battery pack.

Driver electronics for a BLDC motor.

Raspberry Pi's dual-core ARM MCU. The chip on our Stamp.

Winbond 16 MB QSPI flash chip (the part on the Stamp).

Common 3.3 V LDO, 600 mA, in a SOT-23-5 package. JLCPCB Basic part.

3.3 V LDO used on the Solder Party Stamp.

4-channel auto-direction voltage level shifter. Handles both I²C and SPI.

N-channel MOSFET, the classic part for bidirectional I²C level shifting.

TDK InvenSense 9-DoF IMU with onboard magnetometer. The chip you picked.

Bosch 6-DoF IMU, modern, low-power.

TDK 6-DoF IMU, high-precision, used in FPV drones.

Bosch 9-DoF IMU with on-chip sensor fusion.

Asahi Kasei magnetometer die — sits inside the ICM-20948 package.

Square chip with pads on the underside, no visible leads. The RP2040 is a QFN-56.

Small rectangular chip with gull-wing leads on two sides. The W25Q128 is SOIC-8.

Tiny 3- to 8-pin package for small transistors and regulators.

Sizes of surface-mount passives (resistors/caps) in hundredths-of-an-inch. 0603 = 0.06" × 0.03".

The old-school through-hole IC with two rows of pins. Mostly obsolete now.

Chip with solder balls on the underside in a grid. Used for high-pin-count parts.

2.54 mm pitch pins, the classic "breadboard-compatible" connector.

Families of small wire-to-board connectors. PH = 2 mm pitch, SH = 1 mm pitch, XH = 2.5 mm.

4-pin JST-SH I²C connector — chainable, plug-and-play. Same physical connector, both companies use it.

Half-cylinder plated edge of a board, used so a module can be reflow-soldered onto a carrier (like the Stamp).

Components with leads that go through holes in the board, soldered on the other side.

Surface Mount Device / Technology — components with no leads, soldered to pads on top of the board.

Metric screw thread sizes. M2 = 2 mm diameter, M3 = 3 mm. Standard PCB mounting hardware.

Software check of the schematic: unconnected pins, conflicting drivers, missing GND.

Software check of the layout: trace too thin, clearance violations, drill out of fab spec.

Industry-standard file format describing each copper layer of a PCB. What fabs need.

Tells the fab where to drill holes and what diameter.

The parts list — what to populate where.

Says where on the board each part sits (X, Y, rotation). Needed for pick-and-place machines.

The discipline of designing a board so it can actually be built reliably and cheaply.

Cheapest, most common PCB surface finish. Tin-lead or lead-free.

Higher-quality (more expensive) finish. Gold-plated pads.

Chinese PCB fab + assembly house. Cheap, fast, our default.

Similar to JLCPCB. Slightly more expensive, more flexible on options.

The Chinese parts distributor that supplies JLCPCB. Parts are referenced by Cxxxxx codes.

The machine that picks SMD parts off a reel and places them on the PCB before reflow.

The oven step that melts solder paste and bonds SMD parts to the PCB.

The open-source PCB design tool we use.

The headless command-line version of KiCad. The pipeline drives this.

Older Autodesk-owned PCB design tool. Many open-source boards are still in Eagle format.

Industry-standard commercial PCB tool. Expensive, full-featured.

Browser-based PCB tool tied to JLCPCB/LCSC.

Browser-based read-only viewer for KiCad files. We tried it, ended up using SVG instead.

Open-source tool that converts Gerber files into CNC G-code (for DIY PCB milling).

Circuit simulators. SPICE = Simulation Program with Integrated Circuit Emphasis.

TI's online tool that designs a buck/LDO from your specs and outputs schematic + layout.

Analog Devices' equivalent of WEBENCH.

JavaScript 3D library. Used in our preview HTML to render the .glb board model.

3D file format (binary variant is .glb). What kicad-cli exports for our interactive 3D viewer.

Standard 3D CAD format. KiCad exports this for mechanical CAD integration.

USB Flash Format. Drag-and-drop firmware format used by RP2040 / Microsoft.

A common register name in IMU chips — reading it returns a known ID byte that confirms the chip is alive.

ElectroStatic Discharge — the spark when you touch a doorknob. Can fry exposed chip pins.

ElectroMagnetic Interference — noise radiated by or picked up by a circuit.

Regulatory bodies (US / Europe) that certify a product's EMI emissions before sale.

Whether a signal arrives at the receiving end the right shape. Matters at high speeds.

Two traces carrying complementary signals (USB D+/D-, MIPI). Routed equal length, equal spacing.

The "AC resistance" of a trace. For high-speed buses, this must be controlled (e.g. 90 Ω diff pair for USB).

A resistor that holds a pin at a known voltage (high or low) when nothing else is driving it.

An output type that can only pull low. Needs an external pull-up to go high. I²C lines are open-drain.

An output type that can actively drive both high and low. SPI lines are push-pull.

The process of testing a freshly fabbed board step by step until it works.

One fab + bring-up cycle. "v1, v2, v3" = three spins. Costs $35 + 7 days each.

Originally a chip-fab term; informally used for "shipping the design files to the fab."

Pin on the ICM-20948 that selects I2C address. Low = 0x68, high = 0x69. Lets you put two IMUs on the same I2C bus.

"Output Enable" pin on the TXB0104 level shifter. Tying it to VCCA enables the chip, leaving it floating or low keeps the outputs in high-impedance.

An output state where the pin is neither driving high nor low, effectively disconnected from the circuit.

Open-drain: the chip can only pull a line low; it relies on an external pull-up resistor to make it high. Push-pull: the chip can drive both states actively. I2C is open-drain, SPI is push-pull.

Equivalent Series Resistance. A real capacitor isn't perfect; ESR is the tiny resistance in series with it. Matters for LDO stability.

Four ways an SPI bus can sample data, defined by clock polarity and phase. The host and chip must agree. ICM-20948 supports modes 0 and 3.

A single byte (or set of bytes) inside a chip that controls or reports something. Reading register 0x00 of an ICM-20948 returns WHO_AM_I = 0xEA.

Place the board flat and read sensors. Accel Z should be near +1g (gravity), gyro all near zero. If not, something is wrong.

A transistor whose "switch" closes (conducts) when the gate is driven HIGH. Used to pull a pin DOWN to GND in both I²C and the bottom half of an SPI output.

The mirror image. Switch closes when gate is driven LOW. Used to pull a pin UP to VCC in the top half of an SPI output. Also used for reverse-polarity protection.

A P-MOSFET stacked on top of an N-MOSFET. The combination can drive the pin to either VCC or GND. Standard output stage for SPI and almost all modern digital pins.

The three terminals of a MOSFET. Gate = control input. Drain and Source = the two ends of the switch.

The time it takes a capacitor to charge through a resistor. On an I²C bus, this is the pull-up resistor × wire capacitance. Determines how fast a "1" can appear. Smaller R or smaller C = faster bus, but you can only go so small before other things break.

Every wire / PCB trace has a tiny capacitance to ground. Usually negligible, but on long I²C buses it's the thing that limits speed.

Data flows in both directions at the same time. SPI's MOSI and MISO can both be active in one clock cycle.

Only one direction at a time. I²C is half-duplex (SDA carries either direction, never both at once).

The property that any device on an open-drain bus can pull it low without conflict. If two devices try at once, the result is just "low" — no damage.

When two push-pull outputs try to drive the same wire in opposite directions. Shorts VCC to GND. The reason SPI can't be multi-drop.

A protocol-level mechanism in I²C that decides which chip gets the bus when two start talking at the same time. Possible only because of the open-drain wire-OR behavior.

An I²C slave can hold SCL low to ask the master to slow down. Common with chips that need extra processing time per byte.

The text format KiCad uses for .kicad_sch and .kicad_pcb files. LISP-style nested parentheses: (symbol (property "Reference" "U1") ...). Plain text, diff-able, scriptable.

Python library that parses and edits KiCad S-expression files cleanly. The likely workhorse for the agent-native pipeline.

Python library where you describe a schematic as Python code; outputs a netlist for KiCad. Alternative to direct S-expression editing.

A list of every component plus which net (named wire) each pin connects to. The bridge between schematic and layout.

Open-source PCB auto-router. Has a CLI mode, so a script can drive it without anyone opening a GUI.

Any tool that places copper traces between component pins automatically. Quality depends on the bus; OK for low-speed digital, weak for USB/MIPI/DDR.

A KiCad schematic split into sub-sheets that act like functions, with named input/output pins. Used by CapnKernel for main + PSU + level translator.

One file inside a hierarchical schematic. Reusable, scoped.

| true lets a parent shell catch an exit from inside cmd` because the exit only kills the subshell, not the parent. The pipeline bug fix used this.

A section inside every .kicad_sch file that caches copies of every symbol definition the schematic uses. Frozen cache, so the schematic opens even if library files change.

Library mechanism where one symbol inherits its shape, pins, and graphics from another. Keeps library files compact. When embedding, the child must either be flattened or co-exist with its parent in lib_symbols.

Sub-blocks like Symbol_0_1, Symbol_1_1 inside a symbol definition. Hold the rectangle and pins. Different from a hierarchical sub-sheet.

Inside a symbol definition each pin has an (at X Y angle). When the symbol is placed at (Px, Py), the pin lives at (Px+X, Py+Y). To connect a wire or label, the endpoint must be at that exact coordinate.

A schematic label whose name is visible across all sheets. Two pins anywhere with the same global label are the same net. The simplest connection mechanism in a single-sheet design.

A KiCad symbol used to tell ERC "this net is driven from outside the schematic." Sits on any net where only power_in pins exist and there's no power_out pin to satisfy the driven-rail check.

The physical pad pattern on the PCB that matches a chip's package. Stored as .kicad_mod files in libraries like Package_DFN_QFN.pretty/. Lib references look like Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm.

Specctra DSN format — KiCad's export for handoff to external auto-routers like Freerouting. Plain text S-expression. Contains components, layers, nets, and design rules.

Specctra Session — the routed result from Freerouting. KiCad imports it back into the .kicad_pcb to produce the final traces.

Open-source PCB auto-router (Java). Reads DSN, writes SES. Headless mode runs in pure CLI. Needs Java 21+ for v2.x.

A region of solid copper on a layer, tied to a net (usually GND). Replaces individual GND traces; every GND pad connects through the surrounding copper. Standard practice.

A small gap pattern around a pad inside a copper pour. Lets you solder the pad without the whole pour sucking heat away. KiCad does this automatically when pad_connection: thermal.

A group of nets sharing routing rules (track width, clearance). E.g., POWER vs SIGNAL. Freerouting and KiCad respect these.

KiCad's Python API for PCB manipulation. Lives at /Applications/KiCad/KiCad.app/Contents/Frameworks/Python.framework/Versions/3.9/lib/python3.9/site-packages/pcbnew.py. Binary extension, only works with KiCad's bundled Python 3.9.

Python tool from the SKiDL ecosystem that converts a KiCad netlist to a .kicad_pcb. Doesn't yet support the modern (KiCad 10) netlist format.

KiCad layer for the physical board outline. Lines drawn here define the shape JLCPCB will cut.

KiCad layer names for Front (top) copper and Back (bottom) copper.

DRC warning that silkscreen text overlaps a copper pad. Cosmetic — the soldermask will clip it.

DRC error that a net has pins not joined by any trace (or copper pour). The autorouter couldn't fit a route, or a trace got removed. Critical.

DRC error that a trace touches two different nets. Critical. The autorouter sometimes does this when packed tightly.

The count of footprint pads that have a net assigned. The rest are NC pins or mechanical (mounting holes).

The post-routing pass Freerouting does to shorten and clean up traces. Multi-thread mode is documented as broken; always use -mt 1.

A small X symbol on a pin telling KiCad "I'm intentionally leaving this disconnected." Used for pins the chip exposes but your design doesn't need, so ERC stops warning about them.

KiCad's quantised coordinate system. Default 1.27 mm (50 mil). Wires and pins must land on grid points to connect cleanly. Off-grid endpoints can't reliably join.

ERC warning that a wire end or pin is not on the snap grid. Cosmetic-leaning but can cause real connectivity bugs.

ERC error for a label sitting in empty space, not touching any pin or wire. The label isn't connecting anything.

ERC warning that a symbol references a footprint name that doesn't exist in any installed library. Usually a typo or moved footprint.

ERC warning that the embedded copy of a symbol in lib_symbols differs from the live library version. Cosmetic, common across KiCad version changes.

Searching parts by electrical specs (voltage, package, tolerance) instead of by name. What makes a parts database useful vs a flat list.

Parts JLCPCB keeps loaded on assembly machines — no setup fee. "Extended" parts cost ~$3/reel extra per job.

Open-source, daily-updated searchable database of the JLCPCB assembly catalog (by yaqwsx). Web UI + downloadable SQLite.

Getting a trace out of a dense pad field (QFN/BGA) into open board area. Often the hardest part of a route; routers handle it with short "escape stubs" before normal pathfinding.

Autorouter strategy: when a net can't route, tear out the blocking traces and re-route both. The cure for plateauing on congested boards.

The capacitance a crystal needs to see to oscillate on-frequency. Wrong caps pull the frequency; matters for USB timing budgets.

Thin laser-cut steel sheet with holes over each SMD pad; you squeegee solder paste through it before placing parts. Thickness (4-6 mil / 0.12-0.15 mm) sets paste volume.

Question the fab's CAM team sends back before production when your files are ambiguous or out of spec. Has a reply deadline; late reply delays the job.

The fab's engineers who turn your Gerbers into production tooling and raise EQs.

The order and thickness of copper and dielectric layers in a board. Sets trace impedance, so it must match the fab's real material.

Glue-like dielectric between copper layers; the style number sets thickness (2116 ~0.1 mm, 7628 ~0.2 mm).

Test strip on the panel that the fab measures to prove the controlled-impedance traces hit target (e.g. 90 ohm USB, 100 ohm MIPI).

Netlist file the fab uses for electrical test (which pads should connect).

Bare-board electrical test with moving needles; no fixture, fine for prototypes. EasyEDA exports FlyingProbeTesting.json for it.

Drill holes without / with copper inside; exported as separate drill files.

Parts you ship to the assembler yourself because they don't stock them (Sam did this with AR0234 at JLC).

Plated holes cut in half at a module edge so it solders flat onto a carrier (Core1106). Needs enough paste to wick up.

Pre-invoice issued before payment; PCB Power needs 100% advance against it.

KiCad plugin that makes one HTML page showing where every part goes on the board; used while hand-placing parts.

Small file KiCad exports alongside Gerbers describing the stackup, thickness and layer order, so the fab reads intent not guesses.

Open-source tool that pulls an LCSC part's symbol, footprint and 3D model into a KiCad library by its C-number.

Heater that melts solder paste under placed parts all at once; how small batches get assembled in-house.

1961 method: flood outward from the start pin cell by cell until you hit the target, then trace back. Always finds a path if one exists; slow on big boards.

Lee's flood with a sense of direction: explores cells closer to the target first, so it finds the same best path much faster.

The price of a path: length + via penalty + bend penalty + crowding penalty. The router finds the cheapest path, so the cost function decides what "good" means.

How to connect a net with many pins using the least total wire. Routers split a multi-pin net into 2-pin connections using these.

1995 method from FPGA routing: let nets overlap at first, then make crowded spots more expensive each round until everyone negotiates their own space. Its "history cost" works like ant pheromone.

Which connection gets routed first. In sequential routing, early nets grab the best space and block later ones.

The metal spot on a part where it connects to the board; tracks end on pads.

A group of pads that must be electrically joined (one signal, one power rail, ground). CORE3588 has 448.

The dashed "must join" lines KiCad draws for a net before it is routed; the router's to-do list.

A copper line of a chosen width joining pads of one net.

The minimum gap between copper of different nets; set by the fab (0.1 to 0.15 mm on our boards).

One sheet of copper in the board; CORE3588 has four, signals top and bottom, ground in the middle.

A plated hole carrying a track from one layer to another; costs space and a hole in the ground plane.

How a router settles nets that want the same space: order, rip-up and retry, pricing crowded spots, trying many variants.

Cuts free space into rooms bounded by real pads and tracks and searches room to room (Freerouting).

A model that learns to route by scoring millions of its own attempts (Quilter, DeepPCB).

Our in-house router and whole-PCB design journey. Named 3 Nov 2026. Command: ants route board.kicad_pcb.

A test board with every track, via and pour deleted while the parts stay where the human placed them. The router gets the blank problem; the human routing is the reference.

The dashed "must join" line KiCad draws for a net before it is routed; the router's to-do list.

Copper of two different nets touching, so two wires become one. Signal corrupted, or board dead if power meets ground.

How the fab makes copper: it starts with a full sheet and dissolves away everything the design does not keep.

A fab's published list of the smallest gaps, tracks, holes and rings it can make reliably. Our clearance comes from it.

A very fine grid of candidate points (25 to 100 microns) the router searches across, layer by layer. Option A for "seeing".

Testing a candidate track against the real pad and track shapes with exact nanometre math before accepting it.

Lattice search for candidates plus exact geometry checks for legality plus a gridless cleanup; what today's winning routers do.

Cuts free space into rooms bounded by the real pads and tracks and searches room to room (Freerouting, Altium interactive). Option B.

Builds a web between obstacles, decides which gaps a net passes (a rubber band), then pulls it tight into copper. Option C.

A model that learns to route by scoring millions of its own attempts (Quilter, DeepPCB). Option D.

How a router settles nets that want the same space: order, rip-up and retry, pricing crowded spots, trying many variants. Dial 2.

Our frame for any router: Seeing (how it sees free space), Negotiating (how nets settle conflicts), Judging (what "better" means).

Our build order: one net through every stage end to end first, then widen. D12.

Our edge: the AI may change the problem (pin, lane, polarity swaps; part nudges) instead of only solving it. Needs Nidhish's yes. D5.

Deciding where each part physically sits on the board. Done after the schematic, before routing. Sets the puzzle routing has to solve.

A candidate placement shown as a map of where the main parts go. Stage 5 offers two or three.

A small placement change made during routing because the router proved a region could not be routed. Traditional term.

A small capacitor placed right next to a chip's power pin to steady its supply; distance matters, so placement rules exist for it.

An AI that can look at an image and describe or judge it. Useful as a reviewer of a render, not as a router.

Our board library split: research boards we try approaches on; test boards never inspected or tuned on, so results do not overfit.

KiCad's own DRC and ratsnest (via kicad-cli) scoring a routed board; no router scores itself.

A routed board with every connection made and zero DRC errors added. The unit of score in autorouter-bench and PCBWorld.

The cleanup pass that straightens a routed track off the grid into clean 45 degree runs, as short as the rules allow.

Making a group of tracks (for example the lanes of one camera) the same length within a tolerance, so their signals arrive together. Sam's CORE3588 rules set targets like 70.09 mm with a 0.15 mm window.

The difference in arrival time (or length) between the two halves of a pair, or between lanes of a group. KiCad 10 can check it as a rule.

The route the current takes back to its source, usually through the ground plane directly under the track. A gap in the plane under a fast signal forces a detour and causes noise.

Unwanted coupling of a signal into a neighbouring track that runs close and parallel for a distance. Spacing and planes reduce it.

Through via: drilled through the whole board (all our boards). Blind via: from an outer layer to an inner one. Buried via: between inner layers only. Microvia: laser-drilled, tiny, one layer step. Blind, buried and micro cost more to fabricate.

A small zigzag added to a track to lengthen it on purpose, used for length matching.

A plated hole that carries a signal from one side of the board to the other, as opposed to a ground via that ties into the ground plane.

The short tracks that lead each pin of a dense chip out to open board space where it can be routed.

A track the router started but could not finish, so it ends in mid-air and still counts as open.

Where the two wires of a differential pair arrive in the opposite order to the pins they must reach, forcing a crossing.

KiCad redrawing a copper pour so it backs away from any track or via of another net that sits inside it.

The clear ring a plane leaves around a via that passes through it without connecting.

A piece of a pour cut off from the rest, for example by a ring of vias, so it no longer connects anything.

Tying a pad or a surface pour to an inner plane with a short stub and a via.