Software check of the layout: trace too thin, clearance violations, drill out of fab spec.
How it looks
Real geometry: CORE3588 copper, drawn from our board file (2D plan view)
Top copper of CORE3588 beside the module connector J1, drawn from our board file. The light bars on the right are the connector's pads, 0.4 mm apart. DRC checks every gap like this, all over the board.
1One camera signal (amber) leaving the connector for a via. The dark amber band around it is the 0.20 mm keep-away zone: neighbouring copper of other nets stops right at its edge, never inside.
Real data: DRC run on our board file
What our own DRC run on CORE3588 printed (KiCad 10, run on a scratch copy). Every electrical and fab check passes; the 169 notices left are about library drawings, not copper.
How it works
Where it fits
DRC checks the board layout; ERC checks the schematic. The numbers it uses are the clearance and widths from the fab.