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Ants: routing and our own terms (from Nov 2026)

Capability table

A fab's published list of the smallest gaps, tracks, holes and rings it can make reliably. Our clearance comes from it.

How it looks

Real geometry: CORE3588 copper, drawn from our board file (2D plan view)
1231 mm
The rules in copper: CORE3588 top layer, 5 x 3.6 mm, drawn flat from our board file.
Our numbers, from the CORE3588 rule files
THE NUMBERS CORE3588 WAS ROUTED TO (PCB POWER, 4 LAYERS)Gap between copper of two nets0.20 mm0.15 mm next to plain viasTrack width0.12 mm smallest used0.2 mm normalVia0.6 mm ring, 0.3 mm hole0.5 / 0.2 mm on fast pairsHole to another net's track0.25 mm
From PCB Power's published list and our design-rule file (core3588.kicad_pro and core3588.kicad_dru).

How it works

WHAT EACH RULE PROTECTSgap: below this, etching may leave a bridgewidth: thinner tracks may break or vanish in the bathvia: the drill wanders a little; the ring must survive thathole to track: drilling can crack copper nearby

Where it fits

The table sets the clearance and other rules that DRC checks. Designing well inside it is DFM.

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